Datasheet

Section 7 ROM
Page 164 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
7.4.2 Flash Memory Control Register 2 (FLMCR2)
b7
⎯
0
b6
⎯
0
b5
⎯
0
b4
FMRDYIE
0
b3
FMBSYRDIE
0
b2
FMISPE
0
b1
FMSPREQ
0
b0
FMSPEN
0
H'FF0661
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7, 6 ⎯ Reserved ⎯
5 ⎯ Reserved
These bits are read as 0. The write value should
be 0.
⎯
4 FMRDYIE
*
1
*
2
Flash read-ready
interrupt enable
0: The ready interrupt is disabled.
1: The ready interrupt is enabled.
R/W
3 FMBSYRDIE
*
1
*
3
Flash busy-read
interrupt enable
0: The busy-read interrupt is disabled.
1: The busy-read interrupt is enabled.
R/W
2 FMISPE*
4
Suspend-request
enable by interrupt
request
0: Transition to erase-suspend mode by an
interrupt request is disabled.
1: Transition to erase-suspend mode by an
interrupt request is enabled.
R/W
1 FMSPREQ
*
1
*
5
*
6
*
7
Erase suspend 0: Erasure is resumed.
1: Transition to erase-suspend mode is made.
R/W
0 FMSPEN
*
4
*
8
Erase-suspend
enable
0: Erase suspend is disabled.
1: Erase suspend is enabled.
R/W
Notes: 1. For programming the flash memory, set the FMSPEN bit to 1.
2. The FMRDYIE bit is cleared to 0 when the FMCMDEN bit changes from 0 to 1.
3. The FMBSYRDIE bit is cleared to 0 when the FMCMDEN bit changes from 0 to 1.
4. When setting the bit to 1, first clear the bit to 0 and then immediately set the bit to 1; do
not allow any interrupt to be generated between these operations.
5. The FMSPREQ bit is set to 1 when an interrupt is generated if the FMSPEN bit is 1 in
EW1 mode.
6. The FMSPREQ bit is set to 1 when an interrupt is generated if the FMSPEN and
FMISPE bits are 1 in EW0 mode.
7. The FMSPREQ bit is cleared to 0 when the FMRDY bit changes from 0 to 1 upon
completion of E/W.
8. The FMSPEN bit is cleared to 0 when the FMRDY bit changes from 0 to 1 if the
FMSPREQ bit is 0.