Datasheet

Section 7 ROM
Page 162 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
7.4 Register Descriptions
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Flash memory data flash protect register (DFPR)
• Flash memory status register (FLMSTR)
7.4.1 Flash Memory Control Register 1 (FLMCR1)
b7
⎯
0
b6
⎯
0
b5
⎯
0
b4
⎯
0
b3
FMLBD
0
b2
FMWUS
1
b1
FMEWMOD
0
b0
FMCMDEN
0
H'FF0660
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7, 6 ⎯ Reserved ⎯
5, 4 ⎯ Reserved
These bits are read as 0. The write value should
be 0.
⎯
3 FMLBD*
1
*
2
Lock bit disable 0: The lock bits are enabled.
1: The lock bits are disabled.
R/W
2 FMWUS CPU
reprogramming-
instruction unit
select
0: Reprogramming through byte instructions
1: Reprogramming through word instructions
R/W
1 FMEWMOD EW mode select 0: EW0 mode
1: EW1 mode
R/W
0 FMCMDEN
*
1
*
2
*
3
*
4
Flash memory
software
command enable
0: Flash memory software commands are disabled.
1: Flash memory software commands are enabled.
R/W
Notes: 1. When setting the bit to 1, first clear the bit to 0 and then immediately set the bit to 1; do
not allow any interrupt to be generated between these operations.
2. The bit is cleared to 0 when the FMRDY bit changes from 0 to 1.
3. Set the FMEWMOD bit and then set the FMCMDEN bit to 1.
4. When setting the FMCMDEN bit to 1 while the FMEWMOD bit is 0, be sure to execute
the program in the RAM.
FLMCR1 enables/disables reprogramming/erasure, selects the reprogramming/erasure mode,
enables/disables lock bits, and selects the reprogramming unit of the flash memory. For specific
use, see section 7.6, Programming/Erasing.