Datasheet

Section 6 Power-Down Modes
REJ09B0465-0300 Rev. 3.00 Page 149 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
LPCR1
PSCSTP = 0
LPCR1
PSCSTP = 1
Function Active Mode Sleep Mode Active Mode Sleep Mode Standby Mode
IIC2/SSU Functioning Functioning Retained Retained Reset Peripheral
modules
A/D
converter_1,
A/D
converter_2
Functioning Functioning Retained*
4
Retained*
4
Reset
D/A converter Functioning Functioning Functioning Functioning Reset
Notes: 1. The timers are stopped if φ/2 to φ/8192 is selected as the clock source of the event-
generation timer.
2. The timers operate if φ is selected as the count clock. The timers are stopped if φ/2 to
φ/8192 is selected as the count clock.
3. The WDT operates if the low-speed OCO or subclock φsub is selected as its clock
source.
4. The A/D converters operate when A/D conversion time = 43 states (max) is selected.
The A/D converters are retained when the other conversion time is set.
6.2.1 Active Mode
In active mode, the CPU, DTC, and all the on-chip peripheral modules operate on the system
clock φ. The system clock frequency can be selected from among φbase, φbase/2, φbase/4,
φbase/8, φbase/16, φbase/32, φbase/64, and φbase/128 according to the PHI[2:0] setting in LPCR2.
6.2.2 Sleep Mode
When a SLEEP instruction is executed in active mode with the SSBY bit = 0 in LPCR1, a
transition to sleep mode is made. In sleep mode, the CPU is stopped but the DTC and all the on-
chip peripheral modules operate on the system clock. CPU register contents are retained.
When an interrupt is requested, sleep mode is canceled causing a transition to active mode and
interrupt exception handling starts. Sleep mode cannot be canceled if the I bit in CCR is 1 or the
requested interrupt is masked by the interrupt enable bit. After sleep mode is canceled, the high-
speed or low-speed clock is selected as the system clock source depending on the SLEEPRS bit
setting in LPCR1.
When the RES pin is driven low or any other internal reset occurs, sleep mode is canceled causing
a transition to the reset state.