Datasheet

Section 5 Clock Pulse Generator
REJ09B0465-0300 Rev. 3.00 Page 127 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Start
Set oscillation settling time
with STS[3:0] in OSCCSR.
Set PMRJ[1:0] in PMRJ.
Wait for stable oscillation
by polling OSCWEF in OSCCSR.
Set PHIHSEL in SYSCCR to 1.
Set OSCBAKE in BAKCR to 1.
Set as least 6.5 ms of oscillation
settling time according to the
oscillation frequency.
Select the oscillator functions
for PJ0 and PJ1 pins.
OSCWEF is set to 1 after the number
of wait states specified by the STS[3:0] bits
has elapsed after selection of the oscillator
functions for the PJ0 and PJ1 pins.
Setting PHIHSEL to 1 switches
φhigh to φosc.
Setting PHIBSEL to 1 switches
φbase from φlow to φhigh.
Enable the external clock backup
after completion of switching the
system clock.
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
LSI operation is driven by the main oscillator clock.
The LSI operates at the low-speed OCO clock.
[6]
LSI operation is driven by the
main oscillator clock.
Ye s
No
Is the backup function used ?
Set PHIBSEL in LPCR1 to 1.
Figure 5.4 Flowchart of Clock Switching from φloco to φosc (2)