Datasheet

Section 5 Clock Pulse Generator
Page 126 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
5.3.1 Switching System Reference Clock to φosc
Figure 5.3 shows a flowchart of the process in which the system reference clock is switched from
φloco to φosc.
Start
Set oscillation settling time
with STS[3:0] in OSCCSR.
Set PMRJ[1:0] in PMRJ.
Set PHIHSEL in SYSCCR to 1.
Set PHIBSEL in LPCR1 to 1.
LSI operation is stopped over
the settling time for the main
oscillator.
Set OSCBAKE in BAKCR to 1.
Set at least 6.5 ms of oscillation
settling time according
to the oscillation frequency.
Select the oscillator functions
for PJ0 and PJ1 pins.
Setting PHIHSEL to 1 switches
φhigh to φosc.
Setting PHIBSEL to 1 switches
φbase from φlow to φhigh.
Counting is driven by φosc during
the oscillation settling time. LSI operation
remains stopped until the number of
wait states for a stable oscillation has
elapsed. LSI operation with φosc
as the operating clock starts after that.
Enable the external clock backup
after completion of switching the
system clock.
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
LSI operation is driven by the main oscillator clock.
The LSI operates at the low-speed OCO clock.
[6]
LSI operation is driven by the
main oscillator clock.
Ye s
No
Is the backup function used ?
Figure 5.3 Flowchart of Clock Switching from φloco to φosc (1)