Datasheet

Section 5 Clock Pulse Generator
REJ09B0465-0300 Rev. 3.00 Page 121 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
5.2.6 OSC Oscillation Settling Control Status Register (OSCCSR)
b7
OSCWEF
0
b6
⎯
0
b5
⎯
0
b4
⎯
0
b3
1
b2
1
b1
1
b0
1
H'FF06D5
STS[3:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 OSCWEF φosc oscillation
settling wait
state
completed flag
0: Number of wait states for a stable φosc oscillation
has not elapsed.
1: Number of wait states for a stable φosc oscillation
has elapsed.
[Setting condition]
• The number of states specified by the STS[3:0] bits
having elapsed since starting of the main clock
oscillator
[Clearing conditions]
• Switching of the functions of the PJ0 and PJ1 pins
from general I/O to the oscillator functions
• A transition to standby mode while the PJ0 and PJ1
pins are functioning as oscillator pins
• Detection of stoppage of φosc oscillation while the
backup function is enabled.
R
6 to 4 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯
3 to 0 STS[3:0] φosc oscillation
settling time
select 3 to 0
Specifies the number of wait states for a stable φosc
oscillation. For the relationship between assigned
values and the numbers of wait states, see table 5.2.
R/W
• STS3 bit to STS0 bit (φosc oscillation settling time select 3 to 0)
Specifies the number of wait states for a stable φosc oscillation. The count clock is φosc. Table
5.2 shows the relationship between assigned values and the numbers of wait states. If the
system reference clock is φosc when the system returns from the standby mode, or when the
system reference clock is switched to φosc, set these bits so that wait time will be 6.5 ms or
greater depending on the frequency of the oscillator.
The watchdog timer is enabled in the initial state. When switching the clock while the
watchdog timer is enabled, take account of the oscillation settling time in adjusting the
overflow cycle of the watchdog timer.