Datasheet

Section 5 Clock Pulse Generator
REJ09B0465-0300 Rev. 3.00 Page 117 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
0 PHIBSEL φbase clock
source select
0: φlow
1: φhigh
[Setting conditions]
• When 1 is written to this bit.
• When the system returns from sleep mode while
SLEEPRS is 1.
• When the system returns from standby mode
while STBYRS is 1.
[Clearing conditions]
• When 0 is written to this bit.
• When the main oscillator backup is generated
while BAKCKSEL in BAKCR is 0.
• When the system returns from sleep mode while
SLEEPRS is 0.
• When the system returns from standby mode
while STBYRS is 0.
R/W
Notes: A MOV instruction should be used to write to this register.
* Operations of the peripheral modules using the φ clock are not affected by this bit
setting.
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 5 to 2 in this register can be written to when this bit is 1.
• SSBY bit (software standby)
Selects a mode to be entered after the SLEEP instruction is executed.
• PSCSTP bit (PSC divider stop)
Stops the PSC divider circuit when this bit is 1. Peripheral modules using φ/2 to φ/8192 clocks
stop operation. (The register values are retained.)
• SLEEPRS bit (φ source select for recovery from sleep mode)
Selects a clock source to be used when a transition is made from sleep mode to active mode.