Datasheet

Section 5 Clock Pulse Generator
Page 116 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
5.2.3 Power-Down Control Register 1 (LPCR1)
b7
WI
1
b6
WE
0
b5
SSBY
0
b4
PSCSTP
1
b3
SLEEPRS
0
b2
STBYRS
0
b1
⎯
0
b0
PHIBSEL
0
H'FF06D1
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 WI Write inhibit 0: Writing is permitted.
1: Writing is inhibited.
W
6 WE Write enable 0: Writing is disabled.
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at
the same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
R/W
5 SSBY Software standby 0: A transition is made to sleep mode.
1: A transition is made to standby mode.
R/W
4 PSCSTP PSC divider stop 0: PSC divider is operating.
1: PSC divider is stopped*.
R/W
3 SLEEPRS φ source select for
recovery from
sleep mode
0: φlow
1: φhigh
R/W
2 STBYRS φ source select for
recovery from
standby mode
0: φlow
1: φhigh
R/W
1 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯