Datasheet
Section 5 Clock Pulse Generator
REJ09B0465-0300 Rev. 3.00 Page 113 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
1 OSCHLT Main oscillator
stop detect flag
0: The external main oscillator is oscillating.
1: The external main oscillator is stopped.
[Setting condition]
When the external main oscillator is stopped while
OSCBAKE is 1.
R
0 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
Notes: Be sure to use MOV instructions to write values to this register.
* Enable the external clock backup after completion of switching of the system clock from
φloco to φosc. If enabling of the backup function is followed by switching of the system
clock from φloco to φosc, switching of the clock signal may fail due to erroneous
detection by the clock-stop detection circuit. Furthermore, if an application is also using
the backup function in the period of switching of the system clock signal between φlow
and φosc, disable the backup function while flow is in use as the system clock signal.
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 5 to 2 in this register can be written to when this bit is 1.
• OSCBAKE bit (external clock backup enable)
The main oscillator stop detect circuit is enabled when this bit is 1. When this LSI operates at
the external main oscillator clock, the backup function is enabled.
By detecting a φosc stop, the system clock is automatically switched to φlow.
• CKSWIE bit (clock switching interrupt enable)
The main clock switching interrupt requests are enabled when this bit is 1.
• CKSWIF bit (clock switching interrupt enable)
This is a clock switching interrupt request flag.
• OSCHLT bit (main oscillator stop detect flag)
When the OSCBAKE bit is 1, this bit indicates the results of external oscillator stop detection.
This bit, however, simply indicates whether the oscillator is active or not; it does not indicate a
stable oscillation. When OSCBAKE is 0, this bit is always read as 0. An oscillator stop is
detected when the external oscillator is between 0 to 2 MHz.