Datasheet

Section 5 Clock Pulse Generator
REJ09B0465-0300 Rev. 3.00 Page 111 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
The system reference clock (φbase) is the basic clock on which the CPU and on-chip peripheral
modules operate. φbase can be divided by a value from 1 to 128 in the system clock divider, and
the divided clock is supplied as the system clock φ. The system clock φ is divided by a value from
2 to 8192 in the PSC divider, and the divided clock can be supplied to on-chip peripheral modules.
The system clock φ is also divided by a value from 1 to 32 in the φs divider, and the divided clock
can be supplied to the bus master and memory.
After release from a reset, φbase is switched to the low-speed OCO.
5.2 Register Descriptions
• Backup control register (BAKCR)
• System clock control register (SYSCCR)
• Power-down control register 1 (LPCR1)
• Power-down control register 2 (LPCR2)
• Power-down control register 3 (LPCR3)
• OSC oscillation settling control status register (OSCCSR)