Datasheet

Section 5 Clock Pulse Generator
Page 110 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
5.1 Overview
• Choice of three clock sources:
φloco, φsub, and φosc
• Main oscillation backup function
By detecting a φosc stop, it is possible to automatically switch the system clock to φlow.
• Clock switching interrupt function
When the system clock is switched from φosc to φloco, a CPU interrupt can be generated if
enabled.
Figure 5.1 shows a block diagram of the clock pulse generation circuit.
Peripheral
module
CPU
DTC
internal
memory
φs
φ
φ
φ/2
φbase
φbase
φhigh
φlow
φsub
φloco
φosc
φbase/2
φbase/4
φbase/8
φbase/16
φbase/32
φbase/64
φbase/128
φ
φ/2
φ/8192
φ/4
φ/4
φ/8
φ/16
φ/32
φs
divider
PSC
divider
To WDT
To WDT, timer RA, and timer RE
.
.
.
System
clock
divider
High-speed/
low-speed
clock select
circuit
High-
speed
clock
select
circuit
Low-
speed
clock
select
circuit
Duty
correction
circuit
Noise
canceller
Sub-
clock
oscillator
Low-
speed
OCO
Clock pulse generator
X1
X2
OSC1
OSC2
Main
clock
oscillator
Clock select circuit
Figure 5.1 Block Diagram of Clock Pulse Generation Circuit