Datasheet

Section 4 Interrupt Controller
REJ09B0465-0300 Rev. 3.00 Page 105 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
4.6 Usage Notes
4.6.1 Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask interrupt requests, the masking becomes
effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an
instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction,
the interrupt concerned is still enabled on completion of the instruction, and so interrupt exception
handling for that interrupt will be executed after completion of the instruction. However, if there is
an interrupt request of higher priority than that interrupt, interrupt exception handling with the
higher-priority interrupt is executed, and that lower-priority interrupt will be ignored. The same
also applies when an interrupt source flag is cleared to 0. Figure 4.6 shows an example in which
the IRQ0E bit in IER is cleared to 0. The above conflict does not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
Internal
address bus
Internal
write signal
φ
IRQ0E
IRQ0 flag
IRQ0
interrupt signal
IER write cycle by CPU
IRQ0 exception handling
IER address
Figure 4.6 Conflict between Interrupt Generation and Disabling