Datasheet

Section 4 Interrupt Controller
Page 104 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
4.5.4 Interrupt Response Time
Table 4.5 shows interrupt response time, the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine.
Table 4.5 Interrupt Response Times
No. Execution Status
Interrupt Control
Mode 0
Interrupt Control
Mode 2
1 Interrupt priority determination
*
1
3
2 Number of wait states until executing
instruction ends
*
2
1 to 21
3 PC, CCR, EXR stack 2 3
4 Vector fetch 2
5 Instruction fetch
*
3
2
6 Internal processing
*
4
2
Total (using on-chip memory) 12 to 32 13 to 33
Notes: 1. Two states in case of internal interrupt
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch
4. Internal processing after interrupt acceptance and internal processing after vector fetch
4.5.5 DTC Activation by Interrupt
The DTC can be activated by an interrupt request. In this case, the following options are available:
1. Interrupt request to CPU
2. Activation request to DTC
3. Both of the above
For details of interrupt requests that can be used to activate the DTC, see table 4.3 and section 11,
Data Transfer Controller (DTC).