Datasheet

Section 4 Interrupt Controller
Page 92 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 4.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source Interrupt Source
Vector
Number Vector Address*
1
DTCER IPR Priority
RES Pin
WDT
LVD
Reset
1. RES pin reset
2. WDT overflow
3. LVD reset
4. Software reset
0 H'0000 to H'0003 ⎯ ⎯
⎯
Reserved 1 to 4 H'0004 to H'0013 ⎯ ⎯
High
CPU
Trace 5 H'0014 to H'0017 ⎯ ⎯
⎯
Reserved 6 H'0018 to H'001B ⎯ ⎯
External
pin
NMI 7 H'001C to H'001F ⎯ ⎯
TRAPA0 (TRAPA #0
instruction)
8 H'0020 to H'0023 ⎯ ⎯
TRAPA0 (TRAPA #1
instruction)
9 H'0024 to H'0027 ⎯ ⎯
TRAPA0 (TRAPA #2
instruction)
10 H'0028 to H'002B ⎯ ⎯
CPU
TRAPA0 (TRAPA #3
instruction)
11 H'002C to H'002F ⎯ ⎯
⎯
Reserved 12 to 15 H'0030 to H'003F ⎯ ⎯
IFMBSYA (access
when flash memory
busy)
16 H'0040 to H'0043 ⎯ ⎯
FLASH
IFLRDY (flash
memory ready)
17 H'0044 to H'0047 ⎯ IPRA7 and
IPRA6
WDT
IWDT (WDT periodic
interrupt)
18 H'0048 to H'004B ⎯ IPRA5 and
IPRA4
ILVINT1 (low-voltage
detected interrupt 1)
19 H'004C to H'004F ⎯
LVD
ILVINT2 (low-voltage
detected interrupt 2)
20 H'0050 to H'0053 ⎯
IPRA3 and
IPRA2
CPG
ICKSW (clock
switching interrupt)
21 H'0054 to H'0057 ⎯ IPRA1 and
IPRA0
Low