Datasheet

Section 4 Interrupt Controller
Page 90 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
IRQn interrupt
request
IRQnE
IRQnF
S
R
Q
Clear signal
Edge detection
circuit
Noise cancel
circuit
IRQnSCB, IRQnSCA
IRQn input
n = 7 to 0
INCCRn
Figure 4.2 Block Diagram of IRQ7 to IRQ0 Interrupt
4.3.2 Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
• The interrupt priority level can be set by means of IPR.
• The DTC can be activated by a peripheral module interrupt request.
• When the DTC is activated by an interrupt request, it is not affected by the interrupt control
mode or CPU interrupt mask bit.