Datasheet

Section 4 Interrupt Controller
REJ09B0465-0300 Rev. 3.00 Page 89 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
4.3 Interrupt Sources
4.3.1 External Interrupt sources
There are nine external interrupts: NMI and IRQ7 to IRQ0. These external interrupts can be used
to cause the device to exit from standby mode.
(1) NMI Interrupt
The nonmaskable interrupt request (NMI) is the highest-priority interrupt, and always accepted by
the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The
NMIEG bit in INTCR can be used to select whether an interrupt is requested at a rising edge or a
falling edge on the NMI pin.
(2) IRQ7 to IRQ0 Interrupts
Interrupts IRQ7 to IRQ0 are generated by an input signal at pins IRQ7 to IRQ0. IRQ7 to IRQ0
interrupts have the following features:
• Using ISCR, it is possible to select whether an interrupt on the IRQ7 to IRQ0 input pins is
generated by a falling edge, rising edge, or both edges.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 4.2.