Datasheet

Section 4 Interrupt Controller
REJ09B0465-0300 Rev. 3.00 Page 85 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
4.2.5 IRQ Status Register (ISR)
b7
IRQ7F
0
b6
IRQ6F
0
b5
IRQ5F
0
b4
IRQ4F
0
b3
IRQ3F
0
b2
IRQ2F
0
b1
IRQ1F
0
b0
IRQ0F
0
H'FF0524
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 IRQ7F IRQ7 flag R/W
6 IRQ6F IRQ6 flag R/W
5 IRQ5F IRQ5 flag R/W
4 IRQ4F IRQ4 flag R/W
3 IRQ3F IRQ3 flag R/W
2 IRQ2F IRQ2 flag R/W
1 IRQ1F IRQ1 flag R/W
0 IRQ0F IRQ0 flag
[Setting condition]
• When the interrupt edge selected by ISCR occurs.
[Clearing conditions]
• When 1 is read from the bit and then 0 is written to
the same bit.
• When IRQn interrupt exception handling is
executed while falling, rising, or both-edge
detection is set.
• When the DTC is activated by an IRQn interrupt
and the DISEL bit in MRB of the DTC is 0.
R/W