Datasheet

Page 976 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
Item Page Revision (See Manual for Details)
24.5 Compare Mode
Operation
24.5.4 External Trigger Input
Timing
841 Amended
A/D conversion can be externally triggered. When the
EXTRGS, TRGS1, and TRGS0 bits are set to B'001 in
ADCR, external trigger input is enabled at the ADTRG pin.
Section 26 Low-Voltage
Detection Circuits
26.2 Register Descriptions
26.2.1 Low-Voltage Detection
Circuit Control Protect
Register (VDCPR)
859 Amended
Bit Symbol R/W
7 WRI W
26.3 Operation
26.3.1 Power-On Reset
Function
Figure 26.5 Operational
Timing of Power-On Reset
868 Amended
Vcc
Prescaler
reset signal
Internal
reset signal
OVF
128 φloco cycles
Prescaler
counter starts
Reset released
Vdet0
V
LVD0min