Datasheet

Page 970 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
Item Page Revision (See Manual for Details)
18.3.5 Operation through an
Event Link
(2) Counting Event
663 Added
… When the event specified in ELSR8 occurs, event
counter operation proceeds with that event as the source to
drive counting, regardless of the setting of TPSC[2:0] bits in
TRGCR and the STR bit in TRGMDR. …
18.3.6 Digital Filtering
Function for Input Capture
Inputs
Figure 18.22 Block Diagram
of Digital Filter
664 Deleted
φ40
φ/32
φ/8
φ/4
φ/2
φ
φ, φ40
TPSC2 to
TPSC0
DFCK1 and
DFCK0
DFA and DFB
IOA[1:0] and
IOB[1:0]
Sampling clock
φ/32
φ/8
φ
Matching
detecting
circuit
Selecter
Edge
detecting
circuit
C
Latch
DQ
C
Latch
DQ
C
Latch
DQ
C
Latch
D
Q
TGIOA and TGIOB
input signals
C
Latch
D
Q
TCLKB
TCLKA
Section 19 Watchdog Timer
(WDT)
19.2 Register Descriptions
667 Amended
• Timer interrupt control register WD (TICRWD)
19.2.1 Timer Control/Status
Register WD (TCSRWD)
668 Amended
Bit Bit Name Description
3 Timer mode
register WD
lockdown
The TMWD register is write-protected when
this bit is 1. Once this bit is set to 1, this bit
can be cleared only by a reset.
:
2 Timer mode
register WD
write inhibit
:
[Clearing condition]
• When 0 is written to TMWI while
TCSRWE is 1
Section 20 Serial
Communication Interface 3
(SCI3, IrDA)
677 Added
SCI3_2 provides IrDA (Infrared Data Association)
communication waveform transmission/reception according
IrDA standard version 1.0.