Datasheet

REJ09B0465-0300 Rev. 3.00 Page 967 of 982
Sep 17, 2010
Item Page Revision (See Manual for Details)
Section 16 Timer RD
16.2 Register Descriptions
16.2.12 Timer RD I/O Control
Registers (TRDIORA and
TRDIORC)
526 Deleted
Notes: 1. When a GR register functions as a buffer register
for a paired GR register, the settings in the IOA2
and IOB2 bits in TRDIORA and the IOC2 and
IOD2 bits in TRDIORC of both registers should
be the same. The IOA3 bit exists only in
TRDIORA_0.
2. In PWM mode, PWM3 mode, complementary
PWM mode, and reset synchronous PWM mode,
the settings of TRDIORA are invalid.
16.3.9 Buffer Operation 581
Amended
(7) Examples of Buffer Operation
…
Counter clearing by input capture B has been set for
TRDCNT, and falling edges have been selected as the
FTIOB pin input capture input edge. And both rising and
falling edges have been selected as the FTIOA pin
input capture input edge.
…
Figure 16.49 Buffer
Operation (4) (Buffer
Operation in Complementary
PWM Mode CMD1 =1, CMD0
= 0)
584 Amended
FTIOB0
FTIOD0
16.3.10 Timer RD Output
Timing
(2) Output Disable Timing of
Timer RD by External Trigger
586 Amended
When TRDOI is selected for inputs and low level is input to
TRDOI, the master enable bit in TRDOER1 is set to 1 and
the output of timer RD will be disabled.