Datasheet

Page 966 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
Item Page Revision (See Manual for Details)
Section 15 Timer RC
15.2 Register Descriptions
15.2.12 General Registers A,
B, C, and D (GRA, GRB,
GRC, and GRD)
462 Amended
… If the corresponding interrupt-enable bit (the IMIEA,
IMIEB, IMIEC, or IMIED bit) in TRCIER is set to 1 at this
time, an interrupt request is generated. …
15.3 Operation
15.3.4 Digital Filtering
Function for Input Capture
Inputs
481 Amended
Input signals on the FTIOA to FTIOD and TRGC pin can be
input via the digital filters. The digital filter includes three
latches connected in series and a match detector circuit.
Figure 15.22 Block Diagram
of Digital Filter
481 Deleted
φ/40
φ/32
FTCI
φ/8
φ/4
φ/2
φ
φ, φ40
CKS2 to
CKS0
φ/32
φ/8
φ
C
Latch
DQ
C
Latch
D
Q
FTIOA to FTIOD
and TRGC
input signals
C
Latch
DQ
15.3.7 Operation through an
Event Link
(2) Counting Event
486 Added
… When the event specified in ELSR2 occurs, event
counter operation proceeds with that event as the source to
drive counting, regardless of the setting of the CKS[2:0] bits
in TRCCR1 and the CTS bit in TRCMR. …