Datasheet

Section 3 Exception Handling
REJ09B0465-0300 Rev. 3.00 Page 71 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
3.4 Trace Exception Handling
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 4,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by the interrupt masking bit in CCR.
Table 3.3 shows the state of CCR and EXR after execution of trace exception handling. Trace
mode is canceled by clearing the T bit in EXR to 0. The T bit saved on the stack retains its value
of 1, and trace mode resumes when control is returned from the trace exception handling routine
by the RTE instruction. Trace exception handling is not carried out after execution of the RTE
instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 3.3 Status of CCR and EXR after Trace Exception Handling
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
0 Trace exception handling cannot be used.
2 1 ⎯ ⎯ 0
[Legend]
1: Set to 1
0: Cleared to 0
⎯: Retains value prior to execution.