Datasheet

Section 3 Exception Handling
Page 66 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
3.3 Reset
A reset has the highest exception handling priority. When the RES pin goes low, all processing
halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for the
specified time at power-on and during operation, hold the RES pin low for the specified time. A
reset initializes the internal state of the CPU and the registers of on-chip peripheral modules, and
selects low-speed on-chip oscillator as a system clock. The chip can also be reset by detection of
the low-voltage, overflow of the watchdog timer, or software.
The interrupt control mode is 0 immediately after reset.
3.3.1 Reset Sources
This LSI enters the reset state by reset sources listed in table 3.2. If multiple reset sources occur
simultaneously, a reset source having the highest priority will be accepted. A reset source can be
identified by reading the reset source flag register (RSTFR).
For details on a low-voltage detection reset, see section 26, Low-Voltage Detection Circuits. For
details on a watchdog timer overflow reset, see section 19, Watchdog Timer (WDT).
Table 3.2 List of Reset Sources
Reset Source Description Priority
Reset by RES pin This LSI enters the reset state if the RES pin is held low for
at least a specified period.
High
Low-voltage detection
reset
This LSI enters the reset state if the power voltage
becomes the specified voltage or lower.
Watchdog timer overflow
reset
This LSI enters the reset state if the counter in the
watchdog timer overflows.
Software reset This LSI enters the reset state if the SRST bit in RSTCR is
set to 1. Low