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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (14x14) 16-Bit 20 MHz I/O number 69
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Section 3 Exception Handling
REJ09B0465-0300 Rev. 3.00 Page 65 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Section 3 Exception Handling
3.1 Exception Handling Types and Priority
As table 3.1 indicates, exception handling is caused by a reset, trace, NMI interrupt, trap
instruction, or interrupt. Exception handling is prioritized as shown in table 3.1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority. Exception
sources, the stack structure, and operation of the CPU vary depending on the interrupt control
mode. For details on the interrupt control mode, see section 4, Interrupt Controller.
Table 3.1 Exception Handling Types and Priority
Priority Exception Type Start Timing of Exception Handling
High Reset Started immediately after a low-to-high transition at the RES pin,
or by other reset sources. The CPU enters the reset state when
the RES pin is low.
Trace*
1
Started when execution of the current instruction or exception
handling ends, if the trace (T) bit in EXR is set to 1.
NMI Generated when an edge of the NMI pin is input. An NMI
interrupt request has the highest priority among interrupt
requests. It is always accepted regardless of the value of the I bit
in CCR.
Trap instruction*
3
Started by execution of a trap instruction (TRAPA).
Low Interrupt Started when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.*
2
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program
execution state.
3.2 Exception Handling Sources and Vector Table
Different vector addresses are assigned to different exception sources. For details on the exception
sources and their vector addresses, see section 4, Interrupt Controller.