Datasheet
Section 27 List of Registers
REJ09B0465-0300 Rev. 3.00 Page 881 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Section 27 List of Registers
The address list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operation mode. The information is given as shown
below.
1. Register Addresses (address order)
• Registers are listed from the lower allocation addresses.
• Registers are classified by functional modules.
• The data bus width is indicated.
• The number of access states is indicated.
2. Register Bits
• Bit configurations of the registers are described in the same order as the register addresses
(address order).
• Reserved bits are indicated by ⎯ in the bit name column.
• When registers consist of 16 bits, bits are described from the MSB side.
3. Register States in Each Operating Mode
• Register states are described in the same order as the register addresses (address order).
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, see the section on that on-chip peripheral module.