Datasheet

Section 26 Low-Voltage Detection Circuits
Page 876 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(4) Low Voltage Detect Interrupt 1 (LVDI1)
LVDI1 is an interrupt generated by the LVD1 circuit. Figure 26.12 shows the operation timing of
LVDI1.
The LVD1 enters the module-standby state after release from a power-on reset is canceled. To
operate the LVDI1, set the VD1E bit in LD1CRL to 1, wait for 50 μs (t
d(E-A)
) until the detection
voltage and the low-voltage detection circuit 1 operation have stabilized using a software timer,
etc., then clear the VD1MS bit to 0 and set the VD1RE bit to 1 in LD1CRH. After that, the output
settings of I/O ports must be made. To cancel the LVDI1, first the VD1RE bit in LD1CRH should
be cleared to 0 and then the VD1E bit in LD1CRL should be cleared to 0. Figure 26.13 shows the
procedure to set the LVDI1.
When the power-supply voltage falls below Vdet1, the LVDI1 clears the LVDINT1 signal to 0
and the VD1DFS bit in LD1CRH is set to 1. If the VD1DFS or VD1IRCS bit in LD1CRH is 1 at
this time, an LVD1 interrupt request is simultaneously generated. In this case, the necessary data
must be saved in the on-chip flash memory area or external EEPROM, etc, and a transition must
be made to standby mode or sleep mode. Until this processing is completed, the power supply
voltage must be higher than the lower limit of the guaranteed operating voltage.
When the power-supply voltage does not fall below Vdet0 but rises above Vdet1, the LVDI2 sets
the LVDINT1 signal to 1 and set the VD1UF bit in LD2CRH to 1. If the VD1DFS bit in LD1CRH
is 1 or the VD1IRCS bit in LD1CRH is 0 at this time, an LVD1 interrupt request is simultaneously
generated.
If the power supply voltage falls below Vdet0, a power-on reset occurs.