Datasheet

Section 26 Low-Voltage Detection Circuits
Page 874 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(3) Low Voltage Detect Reset 1 (LVDR1)
LVDR1 is a reset generated by the LVD1 circuit. Figure 26.10 shows the operation timing of the
LVDR1.
The LVD1 enters the module-standby state after release from a power-on reset. To operate the
LVDR1, set the VD1E bit in LD1CRL to 1, wait for 50 μs (t
d(E-A)
) until the detection voltage and
the low-voltage detection circuit 1 operation have stabilized using a software timer, etc., then set
the VD1MS and VD1RE bits in LD1CRH to 1. After that, the output settings of I/O ports must be
made. To cancel the LVDR1, first the VD1RE bit in LD1CRH should be cleared to 0 and then the
VD1E bit in LD1CRL should be cleared to 0. Figure 26.11 shows the procedure to set the
LVDR1.
When the power-supply voltage falls below Vdet1, the LVDR1 clears the LVDRES1 signal to 0,
and resets the prescaler. The low-voltage detection reset state remains in place until a power-on
reset is generated. When the power-supply voltage rises above the Vdet1 voltage again, the
prescaler starts counting. It counts 32 φloco cycles, and then releases the internal reset signal.
Note that if the power supply voltage falls below V
LVD1min
= 2.7 V and then rises from that point, the
LVDR1 may not occur. Such a case should be evaluated thoroughly.
If the power supply voltage falls below Vdet0, a power-on reset occurs.
LVDRES1
V
CC
Vdet1
Vdet0
GND
OVF
Prescaler
reset signal
Internal
reset signal
32 φloco cycles
Prescaler
counter starts
Reset released
Figure 26.10 Operation Timing of LVDR1