Datasheet

Section 26 Low-Voltage Detection Circuits
Page 868 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
26.3 Operation
26.3.1 Power-On Reset Function
Figure 26.5 shows the operation timing of the power-on reset function. During the power-on reset
function, the LVD0 circuit monitors the power-supply voltage level to initialize the entire chip.
When the power-supply voltage level rises above Vdet0, the prescaler is released from its reset
state and it starts counting. The OVF signal is generated to release the internal reset signal after
the prescaler has counted 128 φloco cycles. After a power-on reset, the LVD0 reset function is
always enabled.
Vcc
Prescaler
reset signal
Internal
reset signal
OVF
128 φloco cycles
Prescaler
counter starts
Reset released
Vdet0
V
LVD0min
Figure 26.5 Operational Timing of Power-On Reset