Datasheet

Section 25 D/A Converter
REJ09B0465-0300 Rev. 3.00 Page 851 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
25.2.2 D/A Control Register (DACR)
Address:
Bit:
Value after reset:
b7
DAOE1
0
b6
DAOE0
0
b5
⎯
0
b4
⎯
0
b3
⎯
0
b2
⎯
0
b1
⎯
0
b0
⎯
0
H'FF05D6
Bit Symbol Bit Name Description R/W
7 DAOE1 D/A output
enable 1
0: Disables the analog output on channel 1 (DA1).
1: Enables the channel 1 D/A conversion; enables
the analog output (DA1).
R/W
6 DAOE0 D/A output
enable 0
0: Disables the analog output on channel 0 (DA0).
1: Enables the channel 0 D/A conversion; enables
the analog output (DA0).
R/W
5 to 0 ⎯ Reserved These bits are always read as 0 and cannot be
modified.
⎯
Note: In standby mode or module standby mode, the contents of DACR are retained.
• DAOE1 bit and DAOE0 bit (D/A output enable 1 and 0)
These bits control the D/A conversion and analog output.
The event link function can be used to set the DAOE[1:0] bits. When the event specified in
ELSR31 or ELSR32 of the ELC occurs, the corresponding DAOE1 or DAOE0 bit is set to 1,
respectively and the D/A conversion starts.