Datasheet

Section 24 A/D Converter

REJ09B0465-0300 Rev. 3.00 Page 845 of 982

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

24.8 Usage Notes

24.8.1 Module Standby Mode Setting

Operation of the A/D converter can be disabled or enabled using the module standby control

enabled by clearing module standby mode. For details, see section 6, Power-Down Modes.

24.8.2 Permissible Signal Source Impedance

This LSI's analog input is designed so that conversion precision is guaranteed for an input signal

for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the

A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;

if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be

possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided

externally for conversion in single mode, the input load will essentially comprise only the internal

input resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass

filter effect is obtained in this case, it may not be possible to follow an analog signal with a large

differential coefficient (e.g., 5 mV/μs or greater) (see figure 24.11). When converting a high-speed

analog signal or conversion in scan mode, a low-impedance buffer should be inserted.

Equivalent circuit of A/D converter

This LSI

7 pF

Cin =

15 pF

10 kΩ

Low-pass

filter

C to 0.1 µF

Sensor output

impedance

Sensor input

5 kΩ or less

Figure 24.11 Example of Analog Input Circuit