Datasheet

Section 24 A/D Converter
REJ09B0465-0300 Rev. 3.00 Page 841 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 24.7 A/D Conversion Time (Scan Mode)
CKS1 CKS0 Conversion Time (State)
1 0 80
1 40
24.5.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the EXTRGS, TRGS1, and TRGS0 bits are set
to B'001 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge of the
ADTRG pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both
single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure
24.8 shows the timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 24.8 External Trigger Input Timing