Datasheet

Section 24 A/D Converter
Page 840 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(1)
(2)
t
D
t
SPL
t
CONV
Address
φ
Write signal
Input sampling
timing
ADF
Legend:
(1) : ADCSR write cycle
(2) : ADCSR address
t
D
: A/D conversion start delay time
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 24.7 A/D Conversion Timing
Table 24.6 A/D Conversion Time (Single Mode)
CKS1 = 1
CKS0 = 0 CKS0 = 1
Item Symbol
Min Typ Max Min Typ Max
A/D conversion start delay time t
D
3 ⎯ 4 ⎯ 3 ⎯
Input sampling time t
SPL
⎯ 30 ⎯ ⎯ 15 ⎯
A/D conversion time t
CONV
83 ⎯ 84 ⎯ 43 ⎯
Note: Values in the table are the number of states.