Datasheet

Section 24 A/D Converter
REJ09B0465-0300 Rev. 3.00 Page 837 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
24.5 Compare Mode Operation
24.5.1 Single Mode in Compare Mode
In single mode in compare mode, the analog input of one selected channel is compared with the
specified voltage. Operations are as follows. The setting of the channel by the CH[3:0] bits in
ADCSR is the same as that in A/D conversion mode.
1. Comparison between the analog input of the selected channel and the voltage specified by the
VAL[9:0] bits is started when the ADST bit in ADCSR is set to 1 by software or external
trigger input.
2. When the comparison is completed, the result is transferred to a bit corresponding to the
channel.
3. On completion of comparison, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated. In addition, if a condition specified by the
CMPFC1 or CMPFC0 bit is satisfied, the CMPF bit in CMPCSR is set to 1. If the CMPIE bit
is set to 1 at this time, a CMPI interrupt is requested.
4. The ADST bit remains set to 1 during comparison, and is automatically cleared to 0 when
comparison ends. When the ADST bit is cleared to 0 during comparison, the A/D converter
stops operation and enters wait state.
AN0
VAL[9:0]
CMP0 in CMPR
ADST
ADF
Comparison voltage input
Specified voltage
Wait for comparison
Previous comparison result Comparison result
Figure 24.5 A/D Converter Operation in Compare Mode
(When Channel 0 Is Selected in Single Mode)