Datasheet

Section 24 A/D Converter
Page 826 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
24.2.5 Compare Data Register (CMPR)
Address:
Bit:
Value after reset:
b7
CMP7
0
b6
CMP6
0
b5
CMP5
0
b4
CMP4
0
b3
CMP3
0
b2
CMP2
0
b1
CMP1
0
b0
CMP0
0
H'FF05E0, H'FF0600
Bit Symbol Bit Name Description R/W
7 CMP7 Compare data
7
R
6 CMP6 Compare data
6
R
5 CMP5 Compare data
5
R
4 CMP4 Compare data
4
R
3 CMP3 Compare data
3
R
2 CMP2 Compare data
2
R
1 CMP1 Compare data
1
R
0 CMP0 Compare data
0
[Setting condition]
When the voltage of the selected analog input
channel is greater than the voltage set in the
CMPVAL register in compare mode.
[Clearing conditions]
• When the A/D converter operating mode is
changed from A/D conversion mode to compare
mode according to the ADM bit in ADMR
setting.
• When the voltage of the selected analog input
channel is equal to or lower than the voltage set
in the CMPVAL register in compare mode.
R
[Legend]
x: Don't care.
Note: * Only 0 can be written to clear the flag.
CMPR holds the comparison result. CMPR is a read-only register that is assigned to the same
address as ADDR0 and ADDR0_2. CMPR is valid in compare mode.