Datasheet

Section 24 A/D Converter
Page 824 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
1 ADSTCLR ADST clear If ADSTCLR is set to 1 in scan mode, the ADST bit
is automatically cleared to 0 when A/D conversion of
all the selected channels has been completed.
R/W
0 EXTRGS External trigger
select
EXTRGS combined with the TRGS1 and TRGS0
bits selects a trigger signal. For details, see the
above description for the TRGS1 and TRGS0 bits.
R/W
[Legend]
x: Don't care.
Notes: 1. Selected only for the H8S/20223 and H8S/20235 Groups.
2. Selected only for the H8S/20103 and H8S/20115 Groups.
3. Not selected only for the H8S/20103 and H8S/20115 Groups.
4. Select these bits to fall the conversion time within the specified time.
• TRGS[1:0] bits (trigger select 1 and 0)
These bits combined with the EXTRGS bit select enable or disable the A/D conversion start by
a trigger signal.
• CKS[1:0] bits (clock select 1 to 0)
These bits the A/D conversion time.
The conversion time should be set while the A/D conversion is stopped (ADST = 0).