Datasheet

Section 2 CPU
REJ09B0465-0300 Rev. 3.00 Page 59 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
2.7.9 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode.
Table 2.13 Effective Address Calculation
No
1
Offset
1
2
4
r
o
p
31 0
31 23
2
3
Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
4
r
o
p
dis
p
r
op
rm
op
rn
3
1
0
3
1
0
r
o
p
D
on't ca
re
3
1
2
3
3
1
0
Don't care
31
0
disp
31
0
31
0
31
23
31
0
D
on't care
31
23
31
0
Don't care
24
24
24
24
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Register direct (Rn)
General register contents
General register contents
General register contents
General register contents
Sign extension
Register indirect (@ERn)
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
• Register indirect with pre-decrement @-ERn
1, 2, or 4
1, 2, or 4
Operand Size
Byte
Word
Longword
Operand is general register contents.