Datasheet

Section 24 A/D Converter
Page 822 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
3 to 0 CH[3:0] Channel select
3 to 0
When SCANE = 1 and SCANS = 0
0000: AN0 0111: AN4 to AN7
0001: AN0 and AN1 1000: AN8
0010: AN0 to AN2 1001: AN8 and AN9
0011: AN0 to AN3 1010: AN8 to AN10
0100: AN4 1011: AN8 to AN11
0101: AN4 and AN5 11xx: Setting prohibited
0110: AN4 to AN6
When SCANE = 1 and SCANS = 1
0000: AN0 0111: AN0 to AN7
0001: AN0 and AN1 1000: AN8
0010: AN0 to AN2 1001: AN8 and AN9
0011: AN0 to AN3 1010: AN8 to AN10
0100: AN0 to AN4 1011: AN8 to AN11
0101: AN0 to AN5 11xx: Setting prohibited
0110: AN0 to AN6
R/W
[Legend]
x: Don't care.
Notes: * Only 0 can be written in bit 7, to clear the flag.
1. The A/D converter should be stopped (ADST = 0) while the Input channels are being
selected.
2. In unit 2, channels can be selected from four channels AN0_2 to AN3_2. Accordingly,
the CH3 and CH2 bits should be cleared to 0 in unit 2.
ADST bit (A/D start)
Clearing this bit to 0 stops A/D conversion or comparison, and the A/D converter enters wait
state. When this bit is set to 1 by software, timer RC, timer RD (conversion start trigger), or
the ADTRG pin, A/D conversion or comparison starts. This bit remains set to 1 during A/D
conversion or comparison. In single mode, this bit is cleared to 0 automatically when
conversion or comparison on the specified channel ends. In scan mode, conversion continues
sequentially on the specified channels until this bit is cleared to 0 by a reset, a transition to
standby mode or software. ADST is cleared to 0 if A/D conversion or comparison of all the
selected channels has been completed while the ADSTCLR bit is 1.