Datasheet

Section 24 A/D Converter
REJ09B0465-0300 Rev. 3.00 Page 821 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
24.2.2 A/D Control/Status Register (ADCSR)
Address:
Bit:
Value after reset:
b7
ADF
0
b6
ADIE
0
b5
ADST
0
b4
⎯
0
b3
0
b2
0
b1
0
b0
0
H'FF05F0, H'FF0610
CH[3:0]
Bit Symbol Bit Name Description R/W
7 ADF A/D end flag
0: A/D conversion or comparison is in progress.
1: A/D conversion or comparison has been
completed.
[Setting conditions]
• When A/D conversion or comparison ends in
single mode
• When A/D conversion or comparison ends on all
specified channels in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DTC is activated by an ADI interrupt
and ADDR is read
R/W
*
6 ADIE A/D interrupt
enable
0: Disables an ADF interrupt.
1: Enables an ADF interrupt.
R/W
5 ADST A/D start 0: Stops A/D conversion or comparison and places
the A/D converter in the wait state.
1: Starts A/D conversion or comparison.
R/W
4 ⎯ Reserved bit This bit is read as 0. The write value should be 0. ⎯
3 to 0 CH[3:0] Channel select
3 to 0
When SCANE = 0 and SCANS = ×
0000: AN0 0111: AN7
0001: AN1 1000: AN8
0010: AN2 1001: AN9
0011: AN3 1010: AN10
0100: AN4 1011: AN11
0101: AN5 11xx: Setting prohibited
0110: AN6
R/W