Datasheet

Section 23 Hardware LIN
Page 810 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Hardware LIN
Read the Sync Field measurement end flag (SFDCT) from
the LINST register.
SCI3_1
Set the SCI3_1 transfer rate by setting the BRR register.
Perform communications using SCI3_1
(when the timer RA counter underflows,
the SBDCT flag is set).
B
SFDCT = 1?
Yes
SCI3_1
Perform communications using SCI3_1.
Receive the ID field in clock asynchronous serial interface
(UART) mode.
No
Calculate the hardware LIN Sync Field.
The timer RA/HW-LIN interrupt can be used.
(When the timer RA counter underflows,
the SBDCT flag is set).
When the SBE bit in the LINCR register is 1
(the input mask is cancelled upon completion
of Sync Break measurement), timer RA can be
used in timer mode after the SFDCT flag in the
LINST register becomes 1.
Set the appropriate transfer rate according
to the Sync Field measurement results.
Yes
Timer RA
Update the Sync Break width by setting the TRAPRE and
TRATR registers.
Figure 23.8 Header Field Reception Flowchart (3)