Datasheet

Section 23 Hardware LIN
Page 808 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Timer RA
Set to pulse width measurement mode by setting the TMOD[2:0] bits in the
TRAMR register to b'011.
Timer RA
Set the TEDGSEL bit in the TRAIOC register to 0 to measure the low level width
of pulses.
Timer RA
Set the TRAIO pin to RXD by setting the TIOSEL bit in the TRAIOC register to 1.
Timer RA
Select the count source by setting the TCK[2:0] bits in the TRAMR register.
Timer RA
Set the Sync Break width by setting the TRAPRE and TRATR registers.
Hardware LIN
Set to slave mode by setting the MST bit in LINCR register to 0.
Hardware LIN
Start operation by setting the LINE bit in the LINCR register to 1.
Hardware LIN
Select the RXD input mask cancellation timing (upon Sync Break detection or
completion of Sync Field measurement) by setting the SBE bit in the LINCR
register.
Set the count source, TRAPRE
register, and TRATR register
appropriately for the Sync Break
width.
A
For the hardware LIN function,
set the TIOSEL bit in the TRAIOC
register to 1.
Select the mask cancellation
timing of the RXD input to SCI3_1.
When a timing is selected such
that the mask is cancelled upon
Sync Break detection, the Sync Field
signal is also input to SCI3_1.
Hardware LIN
Stop operation by setting the LINE bit in LINCR register to 0.
Hardware LIN
Clear the status flags (bus conflict detection, Sync Break detection, and Sync
Field measurement end) by setting the B2CLR, B1CLR, and B0CLR bits in the
LINST register to 1.
Figures 23.6 Header Field Reception Flowchart (1)