Datasheet
Section 23 Hardware LIN
Page 804 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Timer RA
Set to timer mode by setting the TMOD[2:0] bits in the TRAMR register to b'000.
Timer RA
Set the TEDGSEL bit in the TRAIOC register to 1 to set the initial timer pulse
output level to low.
Timer RA
Set the TRAIO pin to RXD by setting the TIOSEL bit in the TRAIOC register to 1.
Timer RA
Select the count source by setting the TCK[2:0] bits in the TRAMR register.
Timer RA
Set the Sync Break width by setting the TRAPRE and TRATR registers.
Hardware LIN
Set to master mode by setting the MST bit in the LINCR register to 1.
Hardware LIN
Start operation by setting the LINE bit in the LINCR register to 1.
Hardware LIN
Enable/disable the interrupts (bus conflict detection and Sync Break detection)
by setting the BCIE and SBIE bits in the LINCR register.
Hardware LIN
Clear the status flags (bus conflict detection, Sync Break detection, and
Sync Field measurement end) by setting the B2CLR, B1CLR, and B0CLR bits
in the LINST register to 0.
Set the count source,
TRAPRE register, and
TRATR register appropriately
for the Sync Break width.
The Sync Field measurement
end interrupt cannot be used
in master mode.
A
For the hardware LIN function,
set the TIOSEL bit in the TRAIOC
register to 1.
Hardware LIN
Stop operation by setting the LINE bit in the LINCR register to 0.
Figures 23.3 Header Field Transmission Flowchart (1)