Datasheet

Section 23 Hardware LIN
REJ09B0465-0300 Rev. 3.00 Page 803 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
23.3 Operation
23.3.1 Master Mode
Figure 23.2 shows the example of hardware LIN interface operation for transmitting the header
field in master mode. Figures 23.3 and 23.4 show the flowcharts for header field transmission.
The hardware LIN interface operates as follows for header field transmission.
1. When 1 is written to the TSTART bit in TRACR register of timer RA, the hardware LIN keeps
outputting a low level from the TXD pin for the period specified by the TRAPRE and TRATR
registers of timer RA.
2. When timer RA underflows, the hardware LIN inverts the TXD pin output, thus setting the
SBDCT flag in the LINST register to 1. In this case, if the SBIE bit in the LINCR register is
set to 1, the timer RA/HW-LIN interrupt occurs.
3. The hardware LIN interface transmits H'55 using SCI3_1.
4. After completing H'55 transmission, the hardware LIN interface transmits the ID field using
SCI3_1.
5. After completing ID field transmission, the hardware LIN interface performs response field
communications.
TXD pin
Sync Break
1
0
SBDCT flag
in LINST
1
0
Timer RA/
HW-LIN interrupt
1
0
Sync Field IDENTIFIER
1. 2. 3. 4.
5.
Write 1 to the B1CLR bit
in LINST.
Note: The following conditions are assumed:
LINE = 1, MST = 1, SBIE =1.
Figure 23.2 Example of LIN Operation for Transmitting Header Field