Datasheet
Section 23 Hardware LIN
Page 802 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
23.2.2 LIN Status Register (LINST)
Address:
Bit:
Value after reset:
b7
⎯
0
b6
⎯
0
b5
B2CLR
0
b4
B1CLR
0
b3
B0CLR
0
b2
BCDCT
0
b1
SBDCT
0
b0
SFDCT
0
H'FF0519
Bit Symbol Bit Name Description R/W
7, 6 ⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
5 B2CLR BCDCT flag clear The BCDCT flag is cleared when 1 is written to
this bit.
This bit is always read as 0.
R/W
4 B1CLR SBDCT flag clear The SBDCT flag is cleared when 1 is written to
this bit.
This bit is always read as 0.
R/W
3 B0CLR SFDCT flag clear The SFDCT flag is cleared when 1 is written to
this bit.
This bit is always read as 0.
R/W
2 BCDCT Bus conflict
detection flag
0: No bus conflict is detected.
1: Indicates that bus conflict has been detected.
R
1 SBDCT Sync Break
detection flag
0: Sync Bread is not detected.
1: Indicates that Sync Break has been detected.
R
0 SFDCT Sync Field
measurement end
flag
0: Sync Field measurement is not ended.
1: Indicates that Sync Field measurement has
been ended.
R