Datasheet

Section 23 Hardware LIN
REJ09B0465-0300 Rev. 3.00 Page 799 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Section 23 Hardware LIN
The hardware LIN works in cooperation with timer RA and SCI3_1 to provide LIN
communications.
23.1 Overview
• Master mode
Generates Sync Break.
Detects bus conflicts.
• Slave mode
Detects Sync Break.
Measures Sync Field.
Controls Sync Break and Sync Field signal inputs to SCI3_1.
Detects bus conflicts.
Figure 23.1 shows a block diagram of the hardware LIN interface.
RXD pin
TXD pin
LSTART bit
SBE bit
LINE bit
Timer RA
interrupt
TIOSEL = 0
Hardware LIN
TIOSEL = 1
RXD data
Timer RA
underflow signal
BCIE, SBIE,
and SFIE bits
SCI3_1 transfer clock
SCI3_1 TE bit
Timer RA output pulse
SCI3_1 TXD data
MST bit
Timer RA
Sync Field
controller
RXD input
controller
Bus conflict
detector
Interrupt
controller
SCI3_1
Timer RA
Timer RA
Figure 23.1 Block Diagram of Hardware LIN