Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
Page 792 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Start
Clear TE and RE in SSER to 0
Set SSUMS in SSMR2 to 1
Set SCKS in SSMR2 to 1 and
set BIDE, SOOS, CSS1and CSS0,
and MSS in SSCRH
[1]
[2] [2] In bidirectional mode, the BIDE bit is set
to 1 and input/output of the SCS pin is set
by the CSS1 and CSS0 bits.
[1] The MLS bit is cleared to 0 for MSB-first transfer.
The clock polarity and phase are set in the
CPOS and CPHS bits.
Clear MLS in SSMR to 0 and
set CPOS and CPHS, and
CKS2 to CKS0 inSSCRH
Clear ORER in SSSR to 0
Set TE and RE in SSER to 1 and
set RIE, TIE and TEIE, and RSSTP in
SSCRH according to transmission/
reception/transmission and reception
End
Figure 22.10 Initialization in Four-Line Bus Communication Mode