Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
REJ09B0465-0300 Rev. 3.00 Page 789 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(4) Serial Data Transmission and Reception
Data transmission and reception is a combined operation of data transmission and reception which
are described before. Transmission and reception is started by writing data in SSTDR. When the
eighth clock rises while the TDRE bit is set to 1 or the ORER bit is set to 1, transmission and
reception is stopped.
To switch from transmit mode (TE = 1) or receive mode (RE = 1) to transmit and receive mode
(TE = RE = 1), the TE and RE bits should be cleared to 0. After confirming that the TEND,
RDRF, and ORER bits are cleared to 0, set the TE and RE bits to 1.
When the module is released from transmit and receive mode (TE = 1 and RE = 1), setting TE = 0
(and RE = 1) after the SSRDR has been read can cause output of the clock signal. For this reason,
start by setting RE = 0 and only set TE = 0 after that (or set both RE = 0 and TE = 0 at the same
time). When TE = 0 and RE = 1 is subsequently set, only set RE = 1 after changing SRES from 1
to 0.