Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
REJ09B0465-0300 Rev. 3.00 Page 785 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(2) Serial Data Transmission
Figure 22.5 shows an example of the SSU operation for transmission. In serial transmission, the
SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is
set as a slave device, it outputs data in synchronized with the input clock.
When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is
automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the
TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is
generated.
When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to
SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while
the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in
SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is
fixed high.
While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that
the ORER bit is cleared to 0 before transmission.
Figure 22.6 shows a sample flowchart for serial data transmission.
SSCK
SSO Bit 0 Bit 1 Bit 0Bit 7 Bit 7Bit 1
TDRE
TEND
LSI Operation
User
processing
Write data
in SSTDR
Write data
in SSTDR
TXI generated TXI generated TEI generated
One frame One frame
Figure 22.5 Example of Operation in Data Transmission