Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
Page 784 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
22.3.5 Operation in Clocked Synchronous Communication Mode
(1) Initialization in Clocked Synchronous Communication Mode
Figure 22.4 shows the initialization in clocked synchronous communication mode. Before
transmitting and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU
should be initialized.
Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE bits in SSER to 0
Clear SSUMS bit in SSMR2 to 0
Clear CPOS and CPHS bits in SSMR
to 0 and set MLS and CKS2 to CKS0
bits in SSCRH
Set SCKS bit in SSMR2 to 1 and
set MSSS bit in SOOS and SSCRH
Clear ORER bit in SSSR to 0
Set the TE and RE bits in SSER to 1
and set RIE, TIE and TEIE bits, and
RSSTP bit in SSCRH according to
transmission/reception/transmission
and reception
End
Figure 22.4 Initialization in Clocked Synchronous Communication Mode