Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)

Page 780 of 982 REJ09B0465-0300 Rev. 3.00

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

22.2.8 SS Receive Data Register (SSRDR)

Address:

Bit:

Value after reset:

H'FF05CF

SSRDR is an 8-bit register that stores received serial data. When the SSU has received one byte of

serial data, it transfers the received serial data from SSTRSR to SSRDR to end receive operation.

After this, SSTRSR is receive-enabled. As SSTRSR and SSRDR function as a double buffer in

this way, continuous receive operations are possible. SSRDR is a read-only register and cannot be

written to by the CPU. SSRDR is initialized to H'FF. In standby mode, SSRDR is initialized.

22.2.9 SS Transmit Data Register (SSTDR)

Address:

Bit:

Value after reset:

H'FF05CE

SSTDR is an 8-bit register that stores serial data for transmission. SSTDR can be read or written

to by the CPU at all times. When the SSU detects that SSTRSR is empty, it transfers the transmit

data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has

already been written to SSTDR during serial transmission, continuous serial transmission is

possible. If the MLS bit in SSMR is set to 1 and when the data is written to SSTDR, the

MSB/LSB inverted data is read. SSTDR is initialized to H'FF. In standby mode, SSTDR is

initialized.

22.2.10 SS Shift Register (SSTRSR)

Address:

Bit:

Value after reset:

⎯

SSTRSR is a shift register that transmits and receives serial data. SSTRSR is not directly readable

or writable from the CPU. In standby mode, SSTRSR is initialized.