Datasheet

Section 22 Synchronous Serial Communication Unit (SSU)
REJ09B0465-0300 Rev. 3.00 Page 779 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
4, 3 ⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
2 ORER Overrun error flag [Setting condition]
• When the next serial reception is completed
while RDRF = 1
[Clearing condition]
• When 0 is written to this bit after reading 1
R/W
1 ⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
0 CE Conflict error flag [Setting conditions]
• When serial communication is started while
SSUMS = 1 in SSMR2 and MSS = 1 in
SSCRH, the SCS pin input is low
• When the SCS pin level changes from low to
high during transfer while SSUMS = 1 in
SSMR2 and MSS = 0 in SSCRH
[Clearing condition]
• When 0 is written to this bit after reading 1
R/W
Notes: In standby mode, SSSR is reset.
* The DTC clears the peripheral module flags when all of the following three conditions
are satisfied.
1. When the DISEL bit is 0.
2. When the transfer counter (DTC transfer count register A (CRA) in normal mode
and repeat mode, or DTC transfer count register B (CRB) in block mode) is not 0.
3. When chain transfer is not used.
• ORER bit (overrun error flag)
Indicates that the RDRF bit is abnormally terminated in reception because an overrun error has
occurred. SSRDR retains received data before the overrun error occurs and the received data
after the overrun error occurs is lost. When this bit is set to 1, subsequent serial reception
cannot be continued. When the MSS bit in SSCRH is 1, this is also applied to serial
transmission.